? 2004 microchip technology inc. ds11126h-page 1 features ? fast read access time?150 ns cmos technology for low power dissipation - 30 ma active - 100 a standby fast byte write time?200 s or 1 ms data retention >200 years endurance - minimum 10 4 erase/write cycles - automatic write operation - internal control timer - auto-clear before write operation - on-chip address and data latches data polling chip clear operation enhanced data protection -v cc detector - pulse filter - write inhibit 5-volt-only operation organized 512x8 jedec standard pinout - 24-pin dual-in-line package - 32-pin plcc package available for extended temperature ranges: - commercial: 0c to +70c - industrial: -40c to +85c description the microchip technology inc. 28c04a is a cmos 4k non-volatile electrically erasable and programmable read only memory (eeprom). the 28c04a is accessed like a static ram for the read or write cycles without the need of external components. during a ?byte write?, the address and data are latched inter- nally, freeing the microprocessor address and data bus for other operations. following the initiation of write cycle, the device will go to a busy state and automati- cally clear and write the latched data using an internal control timer. to determine when a write cycle is com- plete, the 28c04a uses data polling. data polling allows the user to read the location last written to when the write operation is complete. cmos design and pro- cessing enables this part to be used in systems where reduced power consumption and reliability are required. a complete family of packages is offered to provide the utmost flexibility in applications. package types block diagram 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a7 a6 a5 a4 a3 a2 a1 a0 i /o0 i /o1 i /o2 v vcc a8 nc we oe nc ce i/o7 i/o6 i/o5 i/o4 i/o3 ss a6 a5 a4 a3 a2 a1 a0 nc i /o0 a8 nc nc nc oe nc ce i/o7 i/o6 a7 nc nc nu vc c w e nc i /o1 i /o2 vss nu i /o3 i /o4 i /o5 14 15 16 17 18 19 20 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 dip plcc 28c04a ? pin 1 indicator on plcc on top of package 28c04a i/o0 i/o7 input/output buffers chip enable/ output enable control logic ce oe data protection circuitry a8 y gating 4k bit cell matrix x decoder y decoder a0 data poll auto erase/write timing v cc v ss w e l a t c h e s program voltage generation 28c04a 4k (512 x 8) cmos eeprom obsolete device
28c04a ds11126h-page 2 ? 2004 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc and input voltages w.r.t. v ss ....... -0.6v to + 6.25v voltage on oe w.r.t. v ss ...................... -0.6v to +13.5v output voltage w.r.t. v ss .................-0.6v to v cc +0.6v storage temperature ..........................-65c to +125c ambient temp. with power applied .......-50c to +95c *notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating con- ditions for extended periods may affect device reliability. table 1-1: pin function table name function a0 - a8 address inputs ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs v cc +5v power supply v ss ground nc no connect; no internal connection nu not used; no external connection is allowed table 1-2: read/write operation dc characteristics v cc = +5v 10% commercial (c): tamb = 0c to +70c industrial (i): tamb = -40c to +85c parameter status symbol min max units conditions input voltages logic ?1? logic ?0? v ih v il 2.0 -0.1 v cc +1 0.8 v v input leakage i li -10 10 av in = -0.1v to v cc +1 input capacitance c in 10 pf v in = 0v; tamb = 25c; f = 1 mhz output voltages logic ?1? logic ?0? v oh v ol 2.4 0.45 v v i oh = -400 a i ol = 2.1 ma output leakage i lo -10 10 av out = -0.1v to v cc + 0.1v output capacitance c out 12 pf v in = 0v; t amb = 25c; f = 1 mhz power supply current, active ttl input i cc 30 ma f = 5 mhz (note 1) v cc = 5.5v power supply current, standby ttl input ttl input cmos input i cc ( s ) ttl i cc ( s ) ttl i cc ( s ) cmos 2 3 100 ma ma a ce = v ih (0c to +70c) ce = v ih (-40c to +85c) ce = v cc -0.3 to v cc +1 oe = v cc all inputs equal v cc or v ss note 1: ac power supply current above 5 mhz; 1 ma/mhz.
? 2004 microchip technology inc. ds11126h-page 3 28c04a table 1-3: read operation ac characteristics figure 1-1: read waveforms ac testing waveform: v ih = 2.4v; v il = 0.45v; v oh = 2.0v; v ol = 0.8v output load: 1 ttl load + 100 pf input rise and fall times: 20 ns ambient temperature: commercial (c): tamb = 0c to +70c industrial (i): tamb = -40c to +85c parameter sym 28c04a-15 28c04a-20 28c04a-25 units conditions min max min max min max address to output delay t acc 150 200 250 ns oe = ce = v il ce to output delay t ce 150 200 250 ns oe = v il oe to output delay t oe 70 80 100 ns ce = v il ce to oe high output float t off 050055070ns output hold from address, ce or oe , whichever occurs first t oh 000ns endurance ? 1m ? 1m ? 1m ? cycles 25c, vcc = 5.0v, block mode (note) note: this parameter is not tested but guaranteed by characterization. for endurance estimates in a specific appli- cation, please consult the total endurance model which can be obtained on our bbs or website.
28c04a ds11126h-page 4 ? 2004 microchip technology inc. table 1-4: byte write ac characteristics figure 1-2: programming waveforms ac testing waveform: v ih = 2.4v; v il = 0.45v; v oh = 2.0v; v ol = 0.8v output load: 1 ttl load + 100 pf input rise/fall times: 20 nsec ambient temperature: commercial (c): tamb= 0c to 70c industrial (i): tamb= -40c to 85c parameter symbol min max units remarks address set-up time t as 10 ns address hold time t ah 50 ns data set-up time t ds 50 ns data hold time t dh 10 ns write pulse width t wpl 100 ns note 1 write pulse high time t wph 50 ns oe hold time t oeh 10 ns oe set-up time t oes 10 ns data valid time t dv 1000 ns note 2 write cycle time (28c04a) t wc 1 ms 0.5 ms typical write cycle time (28c04af) t wc 200 s 100 s typical note 1: a write cycle can be initiated be ce or we going low, whichever occurs last. the data is latched on the pos- itive edge of ce or we , whichever occurs first. 2: data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until t dh after the positive edge of we or ce , whichever occurs first. t as t ah t wpl t ds t dh t oes t oeh t dv a ddress ce, we data in oe v ih v il v ih v il v ih v il v ih v il
? 2004 microchip technology inc. ds11126h-page 5 28c04a figure 1-3: data polling waveforms figure 1-4: chip clear waveforms address valid last written address valid t acc t ce t wpl t wph t dv t wc t oe true data ou t data in valid v ih v il data oe we ce a ddress i/o7 out v ih v il v ih v il v ih v il v ih v il v h v ih ce oe w e t s t h t w t s = = 1 s t h = 10ms t w v ih v il v ih v il = 12.0v 0.5v v h
28c04a ds11126h-page 6 ? 2004 microchip technology inc. 2.0 device operation the microchip technology inc. 28c04a has four basic modes of operation?read, standby, write inhibit, and byte write?as outlined in the following table. 2.1 read mode the 28c04a has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. chip enable (ce ) is the power control and should be used for device selection. output enable (oe ) is the output control and is used to gate data to the output pins independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the output toe after the falling edge of oe , assuming that ce has been low and addresses have been stable for at least t acc -t oe . 2.2 standby mode the 28c04a is placed in the standby mode by applying a high signal to the ce input. when in the standby mode, the outputs are in a high impedance state, inde- pendent of the oe input. 2.3 data protection in order to ensure data integrity, especially during criti- cal power-up and power-down transitions, the following enhanced data protection circuits are incorporated: first, an internal v cc detect (3.3 volts typical) will inhibit the initiation of non-volatile programming operation when v cc is less than the v cc detect circuit trip. second, there is a we filtering circuit that prevents we pulses of less than 10 ns duration from initiating a write cycle. third, holding we or ce high or oe low, inhibits a write cycle during power-on and power-off (v cc ). operation mode ce ie we i/o read l l h d out standby h x x high z write inhibit h x x high z write inhibit x l x high z write inhibit x x h high z byte write l h l d in byte clear automatic before each ?write? x = any ttl level. 2.4 write mode the 28c04a has a write cycle similar to that of a static ram. the write cycle is completely self-timed and initi- ated by a low going pulse on the we pin. on the falling edge of we , the address information is latched. on ris- ing edge, the data and the control pins (ce and oe ) are latched. 2.5 data polling the 28c04a features data polling to signal the comple- tion of a byte write cycle. during a write cycle, an attempted read of the last byte written results in the data complement of i/o7 (i/o0 to i/o6 are indetermin- able). after completion of the write cycle, true data is available. data polling allows a simple read/compare operation to determine the status of the chip eliminating the need for external hardware. 2.6 chip clear all data may be cleared to 1's in a chip clear cycle by raising oe to 12 volts and bringing the we and ce low. this procedure clears all data.
28c04a 28c04a product identification system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory o r the listed sales offices. package: l = plastic leaded chip carrier (plcc) p = plastic dip (600mill) temperature blank = 0 c to +70 c range: i =-40 c to +85 c access time: 15 150 ns 20 200 ns 25 250 ns shipping: blank tube t tape and reel ?l? only option: blank = twc = 1ms f = twc = 200 s device: 28c04a 512 x 8 cmos eeprom 28c04a ft?15i /p ? 2004 microchip technology inc. ds11126h-page 7
28c04a ds11126h-page 8 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds11126h-page 9 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of micr ochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance ar e trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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